1. Field of the Invention
This invention relates generally to data transfer control apparatus used in multimedia devices and television game machines and more particularly to a data transfer controller used in a data processing system that utilizes buffering to distribute data from large capacity external storage devices, such as magnetic or optical storage drives, among various data processing components within the processing system.
2. Related Technical Art
An exemplary configuration for prior art information or information processing devices is shown in FIG. 13. Systems such as shown in FIG. 13 employ a central processing unit (CPU) 601, a DMA controller 701, a main storage device 602, and one or more input/output (I/O) devices 702, among other components, etc., all connected to a CPU or CPU data bus 604. In such a configuration, a device that receives appropriate authorization from a control element such as CPU 601 or DMA controller 701, accomplishes data transfer with input/output device 702 or main storage device 602 using the single CPU bus 604.
In an image reproduction device, however, that operates by receiving image data in picture element units and then playing this back, the image remains incomplete when data are missing during an image display period. It is necessary, therefore, that the image playback portion of the device continually receives data during the image display period. For this reason, the prior art required a configuration in which an image playback device was provided with a dedicated frame buffer memory, and writing of data was performed or controlled by the CPU, asynchronously with image display while reading was performed synchronously with image display. In this technique, in order to transfer the required data without undesirable delay in data processing devices such as image playback and sound playback devices used in multimedia systems, each processing device is provided with a dedicated buffer, as in the above example. Here, the data is transferred in advance in a batch transfer mode using the main system memory or the CPU, and then extracted from the buffer memory for use according to the timing of each data processing device using that data.
However, using the prior art technology as shown in FIG. 13, the CPU bus is continuously occupied during data transfer and cannot be used for other operations. Since the CPU determines how data should be directed to each of input/output device, CPU processing time is also dominated by data transfer operations and determinations when this technique is applied to TV game machines and multimedia devices where frequent dynamic data transfer between various devices is required. This results in markedly decreased overall system performance.
Furthermore, in multimedia systems handling large amounts of data, the amount of time during which a CPU bus is occupied by data transfers to data processing devices has greatly increased in the art. Since this increased CPU bus occupation hinders the operation of the overall system, it is difficult to increase the quality of information presentation without performing processing such as temporally thinning the data. Also, various data processing devices require a dedicated buffer memory to receive data without delay, and it is also necessary to adjust the timing with which the data is read. Multimedia systems in particular require more complicated processing, such as matching the timing between image playback devices, sound playback devices, and other data processing devices. It is also necessary in systems that expand compressed image data in order to present it for viewing, to set a fixed length for the data, even if compression efficiency is somewhat sacrificed, and periodically read the data in order to efficiently access memory.